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  • 姓名： 楊冠華
  • 性別： 男
  • 職稱： 副研究員
  • 職務： 
  • 學歷： 博士
  • 電話： 
  • 傳真： 
  • 電子郵件： yangguanhua@ime.ac.cn
  • 所屬部門： 重點實驗室
  • 通訊地址： 北京市朝陽區北土城西路3號

    簡　　歷：

  • 教育背景

    2016.09-2019.06，中國科學院大學，微電子學與固體電子學，博士。

    2012.08-2013.11，香港科技大學，集成電路設計，碩士。

    2007.09-2011.06，西北大學，電子科學與技術，本科。

    工作簡歷

    2013.12-2015.06，Synopsys.inc，模擬集成電路工程師

    2015.07-2016.08，中國科學院微電子研究所，研究實習員。

    2019.07-2022.01，中國科學院微電子研究所，助理研究員

    2022.02-至今，中國科學院微電子研究所，副研究員。

    社會任職：

    研究方向：

  • 先進DRAM存儲器、氧化物薄膜晶體管、三維集成技術

    承擔科研項目情況：

  • 1.國家重點研發計劃青年科學家項目，2023YFB3611600，2023.11-2026.10，項目負責人。

    2.中國科學院青年創新促進會，2022116，2022-2026，項目負責人。

    3.國家自然科學基金青年項目，62004214，2021.01-2023.12，項目負責人。


    代表論著：

  • [1]?Menggan Liu#, Zhi Li#, Wendong Lu#, Kaifei Chen, Jiebin Niu, Fuxi Liao, Zijing Wu, Congyan Lu,?

    Weizeng Li, Di Geng, Nianduan Lu, Chunmeng Dou*, Guanhua Yang*, Ling Li* and Ming Liu, “First?

    Demonstration of Monolithic Three-dimensional Integration of Ultra-high Density Hybrid IGZO/Si SRAM and?

    IGZO 2T0C DRAM Achieving Record-low Latency (<10ns), Record-low Energy (<10fJ) of Data Transfer and?

    Ultra-long data retention (>5000s)”,?2024 Symposium on VLSI Technology, 2024. *通訊作者.?（Best Demo?

    Award in VLSI 2024）

    [2]?Zijing Wu, Jiebin Niu, Congyan Lu, Ziheng Bai, Kaifei Chen, Zhenhua Wu, Wendong Lu, Menggan Liu,?

    Fuxi Liao, Di Geng , Nianduan Lu, Guanhua Yang*, and Ling Li,“Contact Length Scaling in Dual-gate IGZO?

    TFTs”,?IEEE Electron Device Letters,?2024. *通訊作者.（Popular Article in EDL）

    [3]?Kaifei Chen#, Zhengyong Zhu#, Wendong Lu#, Menggan Liu, Fuxi Liao, Zijing Wu, Jiebin Niu, Bok-Moon?

    Kang, Wang Dan, Xie-Shuai Wu, Ming-Xu Liu, Yong Yu, Nan Yang, Gui-Lei Wang, Kan-Yu Cao, Lingfei?

    Wang,Di Geng, Nianduan Lu, Guanhua Yang*, Chao Zhao*, Arokia Nathan, Ling Li* and Ming Liu,“Improved?

    Multi-bit Statistics of Novel Dual-gate IGZO 2T0C DRAM with In-cell VTH Compensation and ΔVSN/ΔVDATA?

    Boosting Technique”,?2023 International Electron Devices Meeting, 2023. *通訊作者.

    [4]?Wendong Lu, Congyan Lu, Guanhua Yang*, Menggan Liu, Kaifei Chen, Fuxi Liao, Xinlv Duan , Nianduan?

    Lu, and Ling Li,“Monolithically Stacked Two Layers of a-IGZO-Based Transistors Upon a-IGZO-Based?

    Analog/Logic Circuits”,?IEEE Transactions on Electron Devices,?2023. *通訊作者.

    [5]?Lihua Xu#, Kaifei Chen#, Zhi Li#, Jingrui Guo, Linfang Wang, Yue Zhao, Shijie Huang, Zhidao Zhou,?

    Chunmeng Dou*, Guanhua Yang*, Lingfei Wang*, Ling Li, Ming Liu, “Reliability-Aware Ultra-Scaled IDG-

    InGaZnO-FET Compact Model to Enable Cross-layer Co-design for Highly Efficient Analog Computing in?

    2T0C-DRAM”,?2023 International Electron Devices Meeting,?2023. *通訊作者.

    [6]?Kaifei Chen, Jiebin Niu, Guanhua Yang*, Menggan Liu, Wendong Lu, Fuxi Liao, Kailiang Huang, XinLv?

    Duan, Congyan Lu, Jiawei Wang, Lingfei Wang, Mengmeng Li, Di Geng, Chao Zhao, Guilei Wang, Nianduan?

    Lu, Ling Li* and Ming Liu, “Scaling Dual-Gate Ultra-thin a-IGZO FET to 30 nm Channel Length with Record-

    high G m,max of 559 μS/μm at V DS =1 V, Record-low DIBL of 10 mV/V and Nearly Ideal SS of 63 mV/dec”,?

    2022 IEEE Symposium on VLSI Technology. *通訊作者. (Invited for Demo Session)

    [7]?Wendong Lu#, Zhengyong Zhu#, Kaifei Chen#, Menggan Liu, Bok-Moon Kang, Xinlv Duan, Jiebin Niu,?

    Fuxi Liao, Wang Dan, Xie-Shuai Wu, Joohwan Son, De-Yuan Xiao, Gui-Lei Wang, Abraham Yoo, Kan-Yu?

    Cao, Di Geng, Nianduan Lu, Guanhua Yang*, Chao Zhao*, Ling Li*, and Ming Liu, “First Demonstration of?

    Dual-Gate IGZO 2T0C DRAM with Novel Read Operation, One Bit Line in Single Cell, ION =1500 μA/

    μm@VDS =1V and Retention Time>300s”,?2022 IEEE International Electron Devices Meeting,?2022. *通訊作

    者. (High Ranked Student Paper)

    [8]?Menggan Liu, Congyan Lu, Guanhua Yang*, Weizhuo Gan, Songang Peng, Zhenhua Wu, Jiebin Niu,?

    Jiawei Wang, Lingfei Wang, Mengmeng Li, Di Geng, Nianduan Lu, Wei Cao, Ling Li, Deji Akinwande and?

    Ming Liu, “Analog Monolayer MoS2 Transistor with Record-high Intrinsic Gain (>100 dB) and Ultra-low?

    Saturation Voltage (<0.1 V) by Source Engineering”,?2021 IEEE Symposium on VLSI Technology,?2021. *通

    訊作者.

    [9]?Guanhua Yang, Jiebin Niu, Congyan Lu, Rongrong Cao, Jiawei Wang, Ying Zhao, Xichen Chuai,?

    Mengmeng Li, Di Geng, Nianduan Lu , Qi Liu, Ling Li*, and Ming Liu*,?“Scaling MoS 2 NCFET to 83 nm with?

    Record-low Ratio of SS ave /SS Ref .=0.177 and Minimum 20 mV Hysteresis”,?2020 International Electron?

    Devices Meeting,?2020.

    [10]Guanhua Yang, Yan Shao, Jiebin Niu, Xiaolei Ma, Congyan Lu, Wei Wei, Xichen Chuai, Jiawei Wang,

    ?Jingchen Cao, Hao Huang, Guangwei Xu, Xuewen Shi, Zhuoyu Ji, Nianduan Lu, Di Geng, Jing Qi, Yun ??Cao, Zhongliu Liu, Liwei Liu, Yuan Huang, Lei Liao, Weiqi Dang, Zhengwei Zhang, Yuan Liu, Xidong Duan, Jiezhi Chen, Zhiqiang Fan, Xiangwei Jiang, Yeliang Wang*, Ling Li*, Hong-Jun Gao, Xiangfeng Duan* & Ming Liu*, “Possible Luttinger liquid behavior of edge transport in monolayer transition metal dichalcogenide crystals”,?Nature Communications,?2020.?


    專利申請：

    獲獎及榮譽：

  • 1.VLSI會議Best Demo Paper Award（2024年）

    2.?IEEE EDL Golden Reviewer（2023年）

    3.Wiley Open Science Excellent Author Program（2023年）

    4.中國科學院微電子研究所十佳先進工作者（2022年）